What you'll learn

IP Verification concepts
Learning System Verilog Language for Verification
Developing System Verilog based testbench and testcases to verify a given IP
A Case study - how to verify an IP using SV

Requirements

Digital fundamentals
Verilog language
Basics of Verification
Linux commands

Description

System Verilog course content is designed for beginners to experts ; The modules can be learnt and practiced in couple of weeks: The detailed course syllabus is as follows: It is split into 2 partsSection I:Session 01 • ASIC flow-Design verification and Verilog Refresh Lab 1 - Verilog Testbench developmentSession 02 •System Verilog Introduction, Data Types Lab 2 - Programs with Various data typesSession 03 •Operators-Control Statements-loopsLab 3- SV Constructs practiceSession 04 •Arrays, QueuesLab 4 - Arrays, Queues Constructs practiceSession 05 •OOPs-Classes-Objects Section II:Session 06 •Randomization and ConstraintsLab 6- RandomizationSession 07 •Inter process CommunicationLab 7- Use of mail box, Semaphores and QueuesSession 08 •Interfaces Lab 8-Use of interfaces, mod port, clocking blockSession 09 • Testbench developmentLab 09- Use of SV constructs for driver/BFMSession 10 •Code and Functional Coverage Lab 10-Simulate an example for coverageVarious example codes are explained in the course. Few of the programs are simulated in the industry standard simulators.A protocol example is also taken and testbench code is developed and test cases are written for the project.The assignment given helps to practice the code writing and further using for test bench and testcase development

Overview

Section 1: Verification in ASIC flow, System Verilog basics - Part I
Lecture 1 ASIC Flow, Verilog Vs System Verilog
Lecture 2 System Verilog Features and Data Types
Lecture 3 SV Tasks, Functions and other advanced data types
Lecture 4 Queues, Arrays
Lecture 5 OOPS Concepts and Classes
Lecture 6 Lab Assignment
Section 2: IP Verification using System Verilog - Part II
Lecture 7 Randomization and Constraints
Lecture 8 Constraints and Inter process communication
Lecture 9 Interface and modports
Lecture 10 System Verilog Testbench for Memory Verification
Lecture 11 Functional Coverage
Lecture 12 Assignment and Project
Internship for BE/MTech (ECE, EEE) students,Engineers who are beginners to System Verilog


Homepage:

https://www.udemy.com/course/ip-verification-using-system-verilog-part-i/